1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method for the same, and more particularly to a semiconductor device with an isolation insulating film tapered and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor memory device has a group of storage elements or memory cells and a peripheral circuit, which are respectively arranged in a memory cell region and a peripheral circuit region on a chip. Also, the size of the semiconductor memory device is mainly dependent upon the size of the memory cell region. For this reason, it is generally designed in such a manner that the memory cells in the memory cell region have patterns finer than the peripheral circuit. In the semiconductor memory device such as a DRAM, an SRAM and a flash EEPROM, high integration is attempted more increasingly in recent years, so that the memory cell is manufactured to have a smaller size.
In such a semiconductor memory device, in order to correctly operate memory cell elements and peripheral circuit elements, an insulating film for physically and electrically separating the neighbor elements from each other is required. Accordingly, the forming technique of such an insulating film is important. The region for separating between the elements is referred to as an isolation region, and the insulating film formed in the isolation region is referred to as an isolation insulating film.
Such an isolation insulating film of a semiconductor memory device is generally formed by a local oxidation of silicon (LOCOS) method. That is, a silicon oxide film having the film thickness of about 50 nm and a silicon nitride film having the film thickness of about 100 to 400 nm are laminated in this order on the surface of a semiconductor substrate. Then, the silicon nitride film on the isolation region is removed using a photo-lithography method and a dry etching method. After that, thermal oxidation is performed to form a silicon oxide film (a field oxide film) as an isolation insulating film in the isolation region.
However, in the LOCOS method, a phenomenon called bird beak occurs in which the isolation insulating film rips into an active region in the boundary between the isolation region and the active region. This obstructs fine formation of a pattern of an element.
A new isolation method is proposed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 4-340767) to solve the above problem. In the new isolation method suitable for the fine formation of a pattern, first, a silicon oxide film of a uniform film thickness is formed on the surface of a silicon substrate. Then, the silicon oxide film on an active region is patterned and removed by a photo-lithography method and a dry etching method. Thus, the isolation insulating film is formed.
The method of manufacturing the isolation insulating film will be described in detail with reference to FIGS. 1A to 1E.
As shown in FIG. 1A, a silicon oxide film layer 901 of a uniform film thickness is first formed by a chemical vapor deposition (CVD) method or a thermal oxidation method on the surface of a silicon substrate 900.
Next, as shown in FIG. 1B, a photo-resist layer is patterned on the isolation region using the photo-lithography method to form a photo-resist pattern 902. Subsequently, the silicon oxide film layer 901 on the active region is removed by the dry etching method using the photo-resist pattern 902 as a mask to produce silicon oxide film patterns 901a.
Next, as shown in FIG. 1C, the photo-resist pattern 902 is peeled off.
Next, as shown in FIG. 1D, a silicon oxide film layer 903 having good coverage is grown on the surface of the substrate, using a low-pressure chemical vapor deposition (LP-CVD) method. As a result, a separation of adjacent silicon oxide film patterns 901a is narrowed smaller than a separation determined based on the lithography method to form an element having fine patterns. Thus, the speeding-up of a circuit is realized.
Next, as shown in FIG. 1E, the silicon oxide film layer 903 is etched back by an anisotropic dry etching method to form side wall insulating films 904 on the side walls of each of the silicon oxide film patterns 901a.
In this way, an element having fine patterns can be formed between the isolation films without any bird beak.
However, when a memory cell element and a peripheral circuit element are formed after the isolation oxide films are formed using the method shown in FIGS. 1A to 1E, the following problem occurs. The problem will be described below with reference to FIGS. 2A to 2D.
As shown in FIG. 2A, the silicon oxide films 1001 with the side wall insulating films 1002 are formed on the silicon substrate 1000 as the isolation insulating films, in the same processes as in FIGS. 1A to 1E.
Next, as shown in FIG. 2B, after a gate oxide film layer 1003 is formed using a thermal oxidation method, a polysilicon layer 1004 is deposited on the surface of the substrate, and then phosphorus ions are implanted.
Further, as shown in FIG. 2C, after a silicon oxide film layer 1005 is formed by a thermal oxidation method, a polysilicon layer 1006 is deposited, and then phosphorus ions are implanted.
Next, as shown in FIG. 2D, the polysilicon layer 1006 is etched to form a control gate 1007. At this time, because there are steep steps in the peripheral circuit region due to the isolation insulating film, the difference in film thickness of the polysilicon film 1006 is between a top flat section and a bottom section. Even if the etching is supposed to be uniformly performed in the state, polysilicon films 1008 would have been left on the side walls of the steps. In this case, since the polysilicon layer 1004 completely fills between the isolation insulating films in the memory cell region to have a flat surface. Therefore, the above etching remainder is not left.
This etching remainder acts as a mask when the oxide film layer 1005 is etched in the subsequent processes to this step. If the polysilicon layer 1004 is etched in this state, the more etching remainder is left in the step portion. The etching remainder causes particles and the production yield decreases. For this reason, if an over-etching is performed to remove the etching remainder, there is the possibility that the lower layer is damaged. There causes a problem in electrical leak and a formation of a short-circuit, resulting in decrease of the production yield.
Also, a gate electrode of 2-layer or 3-layer polysilicon film is generally used in the memory cell region. Therefore, the step between the memory cell region and the peripheral circuit region is large. For this reason, there is a problem in that a manufacture margin in the lithography process and the etching process on the manufacturing way is narrow, resulting in decrease of the production yield.